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inkCard/L5331 Digital - RG354633
LinkCard/L5331 Digital - RG354633

This function block supports the L5331 24VDC Digital LinkCard. For hardware specifications and requirements, please refer to the L5331 Hardware Datasheet. For function block information clink on a topic below.

Description

Configuration Parameters

FB Inputs

FB Outputs


Description

This block supports the L5331 24VDC Digital LinkCard and provides the following functions:

*	16 Logic Inputs/Outputs;

*	16-Bit binary Ordinal Input/Output;

*	1 High-Speed Counter / Frequency Input with the following features:

*	Quadrature, External or Fixed direction sense with negation via FB input;

*	Divide by N (Signed 24-Bit Count and unsigned 23-Bit Divisor);

*	24-bit User counter with:

*	Trigger via a High Speed external input or a standard FB input;

*	2 signed 24-bit comparators;

The Logic and Ordinal output functions share a common 16-bit output register. Ordinals written to the FB for output set the state of all 16 register bits and Logics written to the FB for output set or clear individual register bits. This arrangement means that the "last" state written to a bit "wins" regardless of whether it was in the form of an Ordinal or Logic. SAM Gets on Logic and Ordinal outputs reflect the state of the output register.

A "one" in an output register bit closes a solid-state switch between the external excitation supply and the associated terminal. (The L5331 has self-resetting over-current protection. Please refer to the L5331 hardware datasheet for details.) A "zero" bit opens the corresponding switch leaving the terminal weakly pulled to the external common.

All input functions reflect the actual state of the associated terminal(s) regardless of what the output register contains. Once each millisecond the 16 inputs are sampled. Sampling consists of latch and read operations repeated until the same result is obtained twice in a row. The purpose is to avoid race problems when a transition occurs right when the latch closes.

Logic inputs are individually filtered (according to a configurable timer) to eliminate contact bounce.

The Ordinal Input operates independent of the individual bit-filters using its own configurable filter-period. In all three Ordinal Input aquisition modes, an aquisition triggers a function block output only "on change." Repeated output triggers of the same ordinal do not occur. The Ordinal Input aquisition modes are:

*	When stable (Filtered) - An aquisition occurs when all 16 bits are unchanged for each sample in the configured Ordinal Period. This mode is appropriate when updates during "slew" operations are not desired (binary setpoints, thumbwheels or other switches, etc.)

*	On Sampler (Interpolated) - An aquisition occurs unconditionally at the configured Ordinal Period rate. The result for each aquisition is calculated to be the sum of the stable most-significant bits and 1/2 of the value of the unstable bit range. This mode is appropriate when the bit transitions are not tightly synchronized and changing bits cannot be trusted.

Consider an ordinal as it sweeps upward. Assume it is sampled at the idealized points: $33A and $341. Because the bits' transitions are not tightly synchronized, the actual samples taken could have any value from $300 to $37B with changes occuring in the lowest 7 bits. To maintain the monotonic nature of the signal, the L5331 "splits the difference" and counts the changing bits at 1/2 of their value. This would produce a result of $33F.

*	On Sampler (Simple) - An aquisition occurs unconditionally at the configured Ordinal Period rate. The result for each aquisition is a direct sample of all 16 bits. As in the previous mode, transitions that are not tightly synchronized can cause large uncertainty in the resulting ordinal. This mode is appropriate only in cases where either the bits are are tightly synchronized or the uncertainy is not important.

The high-speed counter(s) and frequency input are clocked off of falling edges on T1. All of these counters are signed and consider the forward direction to count up (more positive) and reverse to count down (more negative). In all three modes, the actual direction used in the FB is the sensed direction, negated if the Dir Negate parameter is enabled. Dir Negate is both configurable and a FB input. Direction sensing operates in one of three configurable modes:

*	Quadrature (T1 & T2) - Sensed direction comes from a standard, 2 phase quadrature signal pair at T1 and T2. Like edges leading on T1 cause the sensed direction to be forward.

*	External (T2) - Sensed direction comes from T2 directly with a high (true) level being considered reverse.

*	Fixed (Fwd) - Sense direction is fixed to be forward and terminal T2 becomes a high-speed trigger & preset for the user counter.

The /N section has a signed 24-bit counter and an unsigned 23-bit N (which is both configurable and is a FB input). Each time the count magnitude exceeds N, a Pulse Dir (true meaning forward) and then a "/N Pulse" one-shot are generated. At the same time, the counter is moved toward zero by N. The goal of the /N system is to provided a robust signal pair that can be counted externally and will never "lose" any counts. The /N counter may output pulses in a direction that differs from the actual or instantaneous direction due to the accumulator effect. (The same is true of the frequency input's sign.)

The User Counter section has a signed 24-bit accumulator, a count-output register and 2 comparators. The counter can be triggered or triggered and preset via a rising edge on FB inputs in any mode. Further, if T2 is not used for hardware direction sense (ie: the Fixed (Fwd) direction sense mode is in use), T2 is a high-speed rising-edge trigger and preset for the user counter. The user counter will roll-over if 2^23 counts occur without a preset occuring.

When triggered, the current count is output (H first) and then optionally set to its preset. The preset and both comparison limits are configurable and settable via FB inputs. (The H portion, if used, must be written first.)

Whenever the user count or either limit changes, the limit comparisons are calculated and (as with other Link logic) a new result is output if it represents a change.

The Frequency Input section operates by counting the cycles that occur during the configurable "sample period", scaling the result according to the configured number of cycles in that period which represents full scale, and generating a FB output value messages at the update rate specified. Being able to select the sample period independent of the update period allows a very large frequency range to be spanned by the 16-bit Value result without generating needlessly high message rates. The sign of the Frequency Input signal indicates the direction which was in effect at the end of the sample period.


Configuration Parameters

Direct Inputs	Logic and Ordinal I/O is discussed in a previous section.

Input # filter	Specifies the delay (in ms) required for each bit input to recognize a level-change. Pulses of less duration will not be seen at the FB bit logic outputs. Must be from 0 to 255ms with zero disabling output messages at the Input # FB output.

Ordinal Trigger	Specifies one of 3 trigger modes for the 16-bit binary representation of the input terminals T1-T16. The modes are discussed in detail in the previous section.

Ordinal Period	Time period (0 - 60000 ms) used to sample the Ordinal Input with zero disabling Ordinal Input messages.

Direction Sense	Direction sensing is discussed in a previous section.

Source	Specifies one of 3 modes of determining the direction for the frequency measurement and high-speed counting. The modes are discussed in detail in the previous section.

Dir Negate	Config Preset for the Dir Negate Input Parameter. If enabled, the actual direction used is the opposite of the sensed direction. This negation applies to all three direction sense modes.

Counter	Counting is discussed in a previous section.

/N Divisor	Config Preset for the unsigned 23-bit Divide by N Divisor. Must be between 1 and 2^23. The Divide by N system is described in a previous section.

Count Preset	Config Preset for the signed 24-bit Count Preset Parameter. Must be between 0 and 2^24.*

C1	Config Preset for the signed 24-bit 24-bit C1 Input Parameter. Must be between 0 and 2^24.*

C2	Config Preset for the signed 24-bit 24-bit C2 Input Parameter. Must be between 0 and 2^24.*

* For added flexibility, these parameters are signed even though ConfigEd treats them as unsigned. To use negative quantities, an understanding of 2's complement binary is required in order to configure the parameters as unsigned numbers in ConfigEd and/or split them into 2 16-bit words for runtime connections.

Frequency Input	Frequency input is discussed in a previous section.

Update Period	Specifies the period (in ms) at which the FB is to generate measured frequency results at the FB output. Zero disables this output. This parameter is internally limited to be equal to or greater than Sample Period.

Cycles / Sample for Full Scale

Specifies the number of cycles (1-65535) within the Sample Period to equate to 100% Frequency.

Sample Period	Specifies the time in ms (1-60000) during which one measurement period's cycles are counted. The update period cannot be shorter than the sample period.


FB Input Parameters

Output #	Sets or clears the associated bit in the output register. Physical outputs are discussed in the previous section.

Output Ordinal	Writes all 16 bits of the output register. Physical outputs are discussed in the previous section.

Dir Negate	If enabled, the actual direction used throughout the FB will be the opposite of the sensed direction. If disabled, they will be the same. See Direction Sensing.

Trig	Logic FB input whose rising edge (ie: false to true transition) triggers the 24-bit User Counter to be latched and sent out the Count FB outputs. The counter value is not changed.

Trig & Preset	The same as trig except that the counter is set to the current Count Preset after the trigger operation is done. In addition to the FB input described here, this function can also be tied to a high-speed physical input T2 if the direction sense mode is Fixed (Fwd) which frees T2 for this purpose.

Count Preset (L/H)	Ordinal FB input to set the 24-bit Count Preset.*

C1 (L/H)	Ordinal FB input to set the 24-bit Comparator 1.*

C2 (L/H)	Ordinal FB input to set the 24-bit Comparator 2.*

N (L/H)	Ordinal FB input to set the 24-bit Divide by N Divisor.*

* 24-bit inputs must be split into a high byte and low word. To facilitate atomic updates, writes to the (H) half are stored in a shadow register until the next write to the L half. This applies to manual changes via SAM as well as runtime changes. The shadow register does not take part in SAM-Gets of these FB inputs. The shadow register is initially zero, so the H portion can be ignored if only a 16-bit range is needed.


FB Output Parameters

Input #	Logic level sensed at terminal # (1-16). Either true or false. These inputs are filtered according to the corresponding Input # filter Config Parameter. See Physical I/O.

Input Ordinal	Terminals T1-T16 are latched and sampled (according to the Ordinal Trigger Config Parameter) as a binary number. See Ordinal Inputs.

Input Frequency	Value (-100% to +100%) which indicates the percent of full-scale frequency seen on terminal T1. The sample period, cycle counts and output update period specified in the Frequency Input Config Parameter section define the full scale frequency. The sign is positive for Forward and negative for Reverse. See Frequency Input.

Dir Fwd	Logic output which indicates whether or not the current direction is forward. This output triggers whenever direction changes occur, unlike the sign of the Input Frequency or the Pulse Dir output which trigger at other times. See Direction Sensing.

Count (L/H)	User Counter output. When triggered (rising edge of Trig or Trig & Preset FB inputs, or T2 if Direction sense mode is Fixed), the current count is output. The H portion will be sent first followed by the L portion. The 24-bit counter is signed.

Count > C1	Logic level which indicates that the signed 24-bit counter is greater than the signed C1 comparator. Changes in the count and C1 can trigger this output.

Count > C2	Logic level which indicates that the signed 24-bit counter is greater than the signed C2 comparator. Changes in the count and C2 can trigger this output.

Pulse Dir Fwd	Logic level sent just prior to the one-shot pulse being sent on /N Pulse. This is used to indicate whether or not the subsequent pulse should be considered Forward. See Divide by N.

/N Pulse	One shot (true followed by false) triggered when the absolute value of the internal signed 24-bit /N accumulator exceeds the unsigned /N divisor.